IBIS Macromodel Task Group

Meeting date: 10 December 2013

Members (asterisk for those attending):
Agilent:                      Fangyi Rao
                            * Radek Biernacki
Altera:                       David Banas
                              Julia Liu
                              Hazlina Ramly
Andrew Joy Consulting:        Andy Joy
ANSYS:                        Samuel Mertens
                              Dan Dvorscak
                              Curtis Clark
                              Steve Pytel
                              Luis Armenta
Arrow Electronics:            Ian Dodd
Cadence Design Systems:       Terry Jernberg
                            * Ambrish Varma
                              Feras Al-Hawari
                            * Brad Brim
                              Kumar Keshavan
                              Ken Willis
Cavium Networks:              Johann Nittmann
Celsionix:                    Kellee Crisafulli
Cisco Systems:                Ashwin Vasudevan
                              Syed Huq
Ericsson:                     Anders Ekholm
IBM:                          Greg Edlund
Intel:                      * Michael Mirmak
Maxim Integrated Products:    Mahbubul Bari
                              Hassan Rafat
                              Ron Olisar
Mentor Graphics:            * John Angulo
                              Zhen Mu
                            * Arpad Muranyi
                              Vladimir Dmitriev-Zdorov
Micron Technology:          * Randy Wolff
                            * Justin Butterfield
NetLogic Microsystems:        Ryan Couts
Nokia-Siemens Networks:       Eckhard Lenski
QLogic Corp.                  James Zhou
SiSoft:                     * Walter Katz
                              Todd Westerhoff
                              Doug Burns
                            * Mike LaBonte
Snowbush IP:                  Marcus Van Ierssel
ST Micro:                     Syed Sadeghi
Teraspeed Consulting Group:   Scott McMorrow
                            * Bob Ross
TI:                           Casey Morrison
                              Alfred Chong
Vitesse Semiconductor:        Eric Sweetman
Xilinx:                       Mustansir Fanaswalla
                              Ray Anderson

The meeting was led by Arpad Muranyi

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Opens:

- Arpad: Reminder that we have one more meeting then a two week break.


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Call for patent disclosure:

- None


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Review of ARs:

- Walter send updated presentation to Mike for posting
  - Done

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New Discussion:

Package Modeling:

- Walter showed a new Package Modeling presentation.
- slide 1:
  - Walter: I gave a quick review in the open forum meeting last week.
- slide 7:
  - Walter: My recommendation is Yes for #1, Touchstone without circuit wrappers.
  - Arpad: The question is if we want to take the time to write it up.

  - Walter recommended Yes for all options under #2.
  - Walter: #2.1 Identifying I/O ports by Signal_Name is optional.
    - #2.2 works because having one port for the PDN model should suffice.
  - Arpad: This is for when a complete pin list is not available?
  - Walter: It is for simplified low frequency power delivery circuits, for example.
  - Walter: #2.3 would be to simplify modeling all DQ signals, for example.
  - Brad: Is #3 two ports?
  - Walter: It can be any number.
  - Brad: This begins to allow for arbitrary circuits - where do we stop?
  - Walter: This probably is the most controversial.
    - IC vendors may like this capability.
  - Bob: We already have this capability though model instantiation.
  - Walter: With 128 DQ or SerDes pins do we want 128 instances in the package model?
  - John: This is like swathing, which can get nasty when coupling is involved.
  - Walter: We should get input from IC vendors on how they deliver coupled models.

  - Bob: For #2.3 Corner Format could be used.
  - Walter: Typ/Min/Max in IBIS is different from AMI Corner.
  - Michael M: We should have the ability to use more than 3 corners.

  - Walter: We need to answer these question to evaluate any syntax.
- slide 8:
  - Walter: Some work will be needed to "include" just a portion of a file.
  - Arpad: Wouldn't that be up to EDA vendors?
  - Walter: IC vendors have to know how to make portable models.
  - Radek: I agree with Arpad that it is an implementation issue.
    - Tools will be able to find the right subckt.

  - Walter: Port naming and ordering must be resolved.
  - Mike L: Will we need something like Supporting_Files?
  - Walter: No, it is possible to find out all the files that will be needed.
  - Bob: Does "Model File Name" involve IBIS models or just IBIS-ISS?
  - Walter: This is for IBIS-ISS and Touchstone only.

  - Michael M: Can we find out if a Touchstone file has the appropriate ports?
    - At least with a wrapper that is known.
  - Walter described TS1 and TS2 differences
  - Michael M: If we go with unwrapped Touchstone we will have to define ports.
  - Walter: An S element could have 6, 7, or 12 nodes.
    - But in all cases it has 6 terminals.
  - Brad: There are always 7 nodes, the 7th is implicit.
    - When I have 100+N ports in my data, how to wrap it?
  - Walter: For uncoupled simulations it can be broken into many small subckts.
    - It can be advantageous to use sNps directly.
  - Brad: Yes, but maybe not for the arbitrary case.
  - Radek: We discussed this for BIRD 144 some time ago.
    - Unused ports were an issue.
    - The IBIS-ISS wrapper takes care of that.
  - Brad: Wrappers would be better than rules.

- slide 7:
  - Walter: This suggests that #2.1.1 would be a No and #2.3.1 would be Sometimes.
  - Radek: It would be more clear to say No.
  - Michael M: We would want to have certain parameters with arbitrary corners, not all.
  - Walter changed some decisions to "take the easy way out".

AR: Walter send updated Package Modeling slides to Mike for posting

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Next meeting: 17 December 2013 12:00pm PT

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IBIS Interconnect SPICE Wish List:

1) Simulator directives